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• W2108246581 abstract "Exponentially tapered interconnect can reduce the dynamic power dissipation of clock distribution networks. A criterion for sizing H-tree clock networks is proposed. The technique reduces the power dissipated by an example clock network by up to 12% while preserving the signal transition times and propagation delays. Furthermore, the inductive behavior of the interconnects is reduced, decreasing the inductive noise. Exponentially tapered interconnects reduce by approximately 20% the difference between the overshoots in the signal at the input of a tree as compared to a uniform tree with the same area overhead." @default.
• W2108246581 created "2016-06-24" @default.
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• W2108246581 date "2004-10-04" @default.
• W2108246581 modified "2023-09-25" @default.
• W2108246581 title "Exponentially tapered H-tree clock distribution networks" @default.
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• W2108246581 doi "https://doi.org/10.1109/iscas.2004.1329343" @default.
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