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- W2108606649 abstract "The authors present a technique for fixed-point digital signal processing using combined bit-serial and bit-parallel arithmetic. Speed performance and hardware complexity are evaluated, and a roundoff error analysis is given when the array is used for realized finite impulse response (FIR) filters. The cycle time needed for the architecture presented is equal to a register setup time plus the delays of a full adder and an AND gate. Even if a carry-save accumulator is used in the arithmetic logic unit (ALU) of the look-up table implementation, the cycle time is still governed by the data access from the look-up table. Moreover, the hardware complexity of the proposed array is only linearly proportional to the order N, whereas the look-up table size is exponentially dependent on N. >" @default.
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- W2108606649 date "1989-01-01" @default.
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- W2108606649 title "A new distributed arithmetic technique for digital signal processing" @default.
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- W2108606649 doi "https://doi.org/10.1109/icsyse.1989.48700" @default.
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