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- W2108767531 abstract "FPGAs are a promising technology for accelerating SAT solvers. Besides their high density, fine granularity, and massive parallelism, FPGAs provide the opportunity for run-time customization of the hardware based on the given SAT instance. In this paper, a parallel deduction engine is proposed for backtrack search algorithms. The performance of the deduction engine is critical to the over-all performance of the algorithm since, for any moderate SAT instance, millions of implications are derived.We propose a novel approach in which, p, the amount of parallelization of the engine is fine-tuned during problem solving in order to optimize performance. Not only the hardware is initially customized based on the input instance, but it is also dynamically modified in terms of p based on the knowledge gained during solving the SAT instance. Compared with conventional deduction engines that correspond to p = 1, we demonstrate speedups in the range of 2.87 - 5.44 for several SAT instances." @default.
- W2108767531 created "2016-06-24" @default.
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- W2108767531 date "2001-01-01" @default.
- W2108767531 modified "2023-10-17" @default.
- W2108767531 title "Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers" @default.
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- W2108767531 doi "https://doi.org/10.1007/3-540-44687-7_33" @default.
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