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- W2108793035 abstract "Branch misprediction penalties depend on branch misprediction rates and branch penalties. Dynamic branch schemes take advantage of hardware to record and predict branch behavior at run-time for reducing branch misprediction rates. Static branch schemes take advantage of scheduling safe instructions into branch delay slots at compile-time for reducing branch penalties. This paper evaluates and compares the performance of various state-of-the-art static and dynamic branch schemes for super-pipelined processors." @default.
- W2108793035 created "2016-06-24" @default.
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- W2108793035 date "1994-01-01" @default.
- W2108793035 modified "2023-09-25" @default.
- W2108793035 title "Minimizing branch misprediction penalties for superpipelined processors" @default.
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- W2108793035 doi "https://doi.org/10.1145/192724.192743" @default.
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