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- W2109124181 abstract "A novel planar interconnect technology based on selective deposition of W has been developed. The conventional approach to metallization, by depositing, patterning and etching of a metal layer, usually results in many steps on the wafer surface. In the W Interconnect Technology (WIT) to be presented, the interconnects are formed by selective deposition of W into oxide channels. Figure 1 outlines the processing sequence to form a level of metallization. A layer of LPCVD Si02 as thick as the desired W layer is deposited. Subsequently, a Si3N4 layer of 100 nm thick is deposited. The channels for the W interconnects are formed by patterning and etching the composite dielectrics. After the photoresist is removed, Si atoms at 40 KeV are implanted. Typically, a dosage as high as l~lO~’cm-~ is required to initiate the deposition of W. A photoresist mask cannot be used because of potential heating problem. The Si3N4 mask is selectively removed in hot H3PO4 solution. The etch rate of SigNq does not appear to be affected by the Si implant. A W film is then electively deposited to fill the Si02 channels [l], which becomes a level of interconnects. This process is repeated to form vias and subsequent levels of interconnects. This W interconnect technology has many desireable features. First, patterning and etching of a metal layer are no longer required. The wafer surface is completely planar after each level of interconnect or via formation] as shown in Figure 2. Only an initial planarization before the first metal is required for multi-level metallization. The adhesion of W on implanted Si02 is very good, with no lifting observed on lines as long as 1000 um. The improved adhesion, over that of blanket CVD W on Si02, is probably due to the Si implant. The W interconnects exhibit a resistivity of 7 pn-cm, which is similar to reported bulk resistivity [2]. A low contact resistivity between W levels is also achieved." @default.
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- W2109124181 date "1986-01-01" @default.
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- W2109124181 title "A planar multi-level tungsten interconnect technology" @default.
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- W2109124181 doi "https://doi.org/10.1109/iedm.1986.191321" @default.
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