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- W2109303919 abstract "This paper proposes a new method for reducing the test length for digital circuits by adopting an architecture derived from the popular scan approach. An evolutionary optimization algorithm is exploited to find the optimal solution. The proposed approach was tested on the ISCAS89 standard benchmarks and the experimental results show its effectiveness." @default.
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- W2109303919 date "2002-09-09" @default.
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- W2109303919 title "Reducing test application time through interleaved scan" @default.
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- W2109303919 doi "https://doi.org/10.5555/827246.827387" @default.
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