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- W2110101554 abstract "This paper describes the architectural and organizational tradeoffs made during the design of the MultiTitan, and provides data supporting the decisions made. These decisions covered the entire space of processor design, from the instruction set and virtual memory architecture through the pipeline and organization of the machine. In particular, some of the tradeoffs involved the use of an on-chip instruction cache with off-chip TLB and floating-point unit, the use of direct-mapped instead of associative caches, the use of 64-bit vs. 32-bit data bus, and the implementation of hardware pipeline interlocks." @default.
- W2110101554 created "2016-06-24" @default.
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- W2110101554 date "1989-01-01" @default.
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- W2110101554 title "Architectural and organizational tradeoffs in the design of the MultiTitan CPU" @default.
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- W2110101554 doi "https://doi.org/10.1145/74925.74957" @default.
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