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- W2110456332 abstract "A 3-8 GHz delay-locked loop (DLL) with cycle jitter calibration is presented. To lower the operation frequency of a voltage-controlled delay line (VCDL), this DLL adopts the dividers, an edge combiner, and the multiple VCDLs. A duty cycle correction circuit is presented to maintain the output duty cycle of 50%. This DLL has been fabricated in 90-nm CMOS process. The measured peak-to-peak jitters at 8 GHz are 11.44 and 6.67 ps before and after calibration, respectively. The power dissipation at 8 GHz is 18 mW for a supply voltage of 1.2 V, and the measured output duty cycle variation is less than 3%." @default.
- W2110456332 created "2016-06-24" @default.
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- W2110456332 date "2008-11-01" @default.
- W2110456332 modified "2023-09-27" @default.
- W2110456332 title "A 3–8 GHz Delay-Locked Loop With Cycle Jitter Calibration" @default.
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- W2110456332 doi "https://doi.org/10.1109/tcsii.2008.2002561" @default.
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