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- W2110578625 abstract "Finite state machines (FSM) are a basic component in hardware design; they represent the transformation between inputs and outputs for sequential designs. FSMs can be represented graphically, which would help the designer to visualize and design in a more efficient way; on the other hand the designer requires a fast direct way to convert the visualized design to hardware description language (HDL) code directly in order to simulate and implement it for synthesis and analysis. In this paper, we present a tool which, starting from a graphical FSM representation, produces a behavioral HDL code which can be directly analyzed and synthesized." @default.
- W2110578625 created "2016-06-24" @default.
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- W2110578625 date "2004-11-12" @default.
- W2110578625 modified "2023-10-01" @default.
- W2110578625 title "A tool converting finite state machine to VHDL" @default.
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- W2110578625 doi "https://doi.org/10.1109/ccece.2004.1347584" @default.
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