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- W2111159097 abstract "We report on the architecture and experimental characterization of a small-footprint optoelectronic receiver for parallel arrays of optical interconnects. The receiver is designed and fabricated in the 0.5-/spl mu/m silicon on sapphire CMOS technology. The circuit design exploits the properties of MOS transistors with three different threshold voltages and the insulating substrate to achieve a low-power, high-speed and compact circuit. The design attains a 7-pJ energy per bit transduction cost when operated at 1 Gbit/s data rates." @default.
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- W2111159097 date "2005-02-01" @default.
- W2111159097 modified "2023-09-23" @default.
- W2111159097 title "A low-power silicon on sapphire CMOS optoelectronic receiver using low- and high-threshold devices" @default.
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- W2111159097 doi "https://doi.org/10.1109/tcsi.2004.840289" @default.
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