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• W2111285148 abstract "A new Continuous-Time (CT) sigma-delta modulator (SDM) based on the well-known asynchronous SDM is proposed in this paper. To this end, the flash quantizer and the digital-to-analog converter (DAC) in a multibit (MB) CT-SDM clocked at a rate f <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>max</sub> are replaced by a single-bit (SB) comparator with hysteresis clocked at a higher rate f <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>s</sub> and a SB-DAC, respectively. By proper selection of the hysteresis in the comparator and the ratio F = f <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>s</sub> /f <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>max,</sub> the performances of both modulators are shown to be equivalent. The comparator with hysteresis and the loop filter produce, in the modulator output, a limit cycle of frequency /max which is modulated by the input signal. Therefore, the modulator output can be considered to be a pulsewidth (PW) modulated signal with a frequency approximately equal to /max, and the proposed modulator is called a PW-SDM. Despite the high sampling rate of the comparator output, the integrators and the SB-DAC of the proposed modulator have the same speed requirements as those of the equivalent conventional MB-SDM. On the other hand, in the proposed modulator there are not MB (analog-to-digital or digital-to-analog) converters. Therefore, for a given set of specifications, the proposed PW-SDM is expected to consume less power and area than its equivalent conventional MB modulator." @default.
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• W2111285148 date "2008-04-01" @default.
• W2111285148 modified "2023-09-27" @default.
• W2111285148 title "Continuous-Time Sigma–Delta Modulator With an Embedded Pulsewidth Modulation" @default.
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• W2111285148 doi "https://doi.org/10.1109/tcsi.2008.919764" @default.
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