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- W2111643374 abstract "Layout options for CMOS ESD diodes' p-n junction geometry and metal routing are investigated in this paper. Experiments are performed using 90- and 180-nm technologies. Using the figures of merit ICP/C and R ON * C, it is shown that twin-well stripe diodes with nonminimum diffusion width and high-level broadside routing are optimum for gigahertz-frequency I/Os. In addition, the suitability of ESD diodes formed with the isolated P-well/deep N-well diffusions available in triple-well technologies is evaluated for high-speed I/O applications." @default.
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- W2111643374 date "2009-09-01" @default.
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- W2111643374 title "Layout Optimization of ESD Protection Diodes for High-Frequency I/Os" @default.
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- W2111643374 doi "https://doi.org/10.1109/tdmr.2009.2025956" @default.
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