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- W2111802090 abstract "Minimal test sets have the property that each input test vector tests simultaneously several faults in a circuit. Existing techniques use Boolean simplification or Karnaugh maps to achieve minimization. The authors present two new methods, one of which is a simple design by inspection technique and the other is a graphical technique. The process of minimization has been simplified by adopting the unique approach of first finding all the faults that can be detected by a single test. >" @default.
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- W2111802090 date "2002-12-10" @default.
- W2111802090 modified "2023-09-26" @default.
- W2111802090 title "Optimal test set for stuck-at faults in VLSI" @default.
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- W2111802090 doi "https://doi.org/10.1109/glsv.1991.143950" @default.
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