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- W2112489225 abstract "XDLCoreGen is described, a module generator framework which directly generates placed and routed hard macros in XDL. XDLCoreGen is intended to be used in a rapid prototyping flow such as HM Flow, which achieves short FPGA implementation times by bypassing the conventional Xilinx tool flow and directly assembling designs from pre-built hard macros. The structure of XDLCoreGen is described and its unique cache-based router is highlighted as a key component to achieving extremely fast module generation times. Testing results are provided to demonstrate XDLCoreGen's ability to generate fully placed and routed hard macros in milliseconds." @default.
- W2112489225 created "2016-06-24" @default.
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- W2112489225 date "2011-09-01" @default.
- W2112489225 modified "2023-09-25" @default.
- W2112489225 title "XDL-Based Module Generators for Rapid FPGA Design Implementation" @default.
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- W2112489225 doi "https://doi.org/10.1109/fpl.2011.22" @default.
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