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- W2113017564 abstract "We have demonstrated on-chip learning in an array of floating-gate MOS synapse transistors. The array comprises one synapse transistor at each node, and normalization circuitry at the row boundaries. The array computes the inner product of a column input vector and a stored weight matrix. The weights are stored as floating-gate charge; they are nonvolatile, but can increase when we apply a row-learn signal. The input and learn signals are digital pulses; column input pulses that are coincident with row-learn pulses cause weight increases at selected synapses. The normalization circuitry forces row synapses to compete for floating-gate charge, bounding the weight values. The array simultaneously exhibits fast computation and slow adaptation: The inner product computes in 10 /spl mu/s, whereas the weight normalization takes minutes to hours." @default.
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- W2113017564 date "1997-01-01" @default.
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- W2113017564 title "A floating-gate MOS learning array with locally computed weight updates" @default.
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- W2113017564 doi "https://doi.org/10.1109/16.644652" @default.
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