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- W2113036231 abstract "We describe a method for performance analysis of large software systems that combines a fast instruction-set simulator with off-line detailed analysis of segments of the execution. The combination is faster than straight cycle-accurate simulation, simpler and more flexible than techniques relying on hardware monitoring, and accurate. Specifically, the instruction-set simulator running at a slowdown of around 50, maintains enough target state throughout the execution that an arbitrarily collected segment of the instruction trace is sufficient input for a post-processing, cycle-accurate model of the processor and memory hierarchy. We present a case study to support our contention that a reduced state is sufficient as input to a cycle-accurate simulator. We use a commercial M88110-based prototype system as a reference point, and show that for three trace segments, the cycle-accurate post-processing gives reliable data to do system optimization." @default.
- W2113036231 created "2016-06-24" @default.
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- W2113036231 date "2002-11-22" @default.
- W2113036231 modified "2023-09-26" @default.
- W2113036231 title "A hybrid simulation approach enabling performance characterization of large software systems" @default.
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- W2113036231 doi "https://doi.org/10.1109/mascot.1997.567585" @default.
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