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- W2113096076 abstract "In this paper, we discuss the Implementation of a low bit-rate linear prediction base-band coder on a bipolar signal processor having a processing capacity of 10 millions of instructions per second (MIPS). We show that the implementation of our algorithm requires less than 5 MIPS, with a ROS occupancy less than 5 K instructions. Some quality evaluation tests are also reported, and show that this type of coder operating at 7.2 kbps, provides a good communications quality, an intelligibility which is sufficient for most of telephony applications, and a perfect speaker recognition (natural voice)." @default.
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- W2113096076 date "2005-03-24" @default.
- W2113096076 modified "2023-09-23" @default.
- W2113096076 title "Voice excited predictive coder (VEPC) implementation on 10 MIPS signal processor" @default.
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- W2113096076 doi "https://doi.org/10.1109/icassp.1984.1172491" @default.
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