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- W2113113185 abstract "This paper presents a heuristic technique based on Particle Swarm Optimization (PSO) for finding the router positions from the available positions within the chip floor plan, so that the communication cost between cores is minimized, satisfying link length and router port constraints. Comparison with regular mesh-based NoC architectures and with custom architectures having routers positioned at the corners of the cores have been carried out. The results show significant reduction in communication cost." @default.
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- W2113113185 date "2011-07-01" @default.
- W2113113185 modified "2023-10-18" @default.
- W2113113185 title "Flexible Router Placement with Link Length and Port Constraints for Application-Specific Network-on-Chip Synthesis" @default.
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- W2113113185 doi "https://doi.org/10.1109/isvlsi.2011.26" @default.
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