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- W2113148102 abstract "The main aim of our research is to investigate the influence of SEU on a digital circuit implemented in FPGA. The FPGA resources occupied by design are divided into several groups. SEU impact is investigated for each group. To make a real dependability model the real effects of injected errors and faults have to be studied. The SEU emulator deals with single-bit change in bitstream. Emulation is performed in the user-selected area. Look-Up-Tables, cell interconnections, cell-to-bus connections and routing resources are considered. Other FPGA resources are not considered. Combinatorial circuits and MCNC benchmarks were measured due to our knowledge of FPGA resource limitation. All tests were performed on Atmel FPSLIC architecture." @default.
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- W2113148102 date "2008-01-01" @default.
- W2113148102 modified "2023-09-26" @default.
- W2113148102 title "Experimental SEU Impact on Digital Design Implemented in FPGAs" @default.
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- W2113148102 doi "https://doi.org/10.1109/dsd.2008.119" @default.
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