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- W2113231699 abstract "Low density parity check (LDPC) codes are used in various communication standards. However, LDPC decoders are complex and power hungry. In this paper, we present an energy-efficient LDPC decoder based on statistical error compensation (SEC). Three different size LDPC codes, (50,25), (800,400), and (1800,900) were implemented with 5 iterations/block. Circuit simulations in a commercial 45nm process show that the SEC based LDPC decoder can operate at a supply voltage up to 38% less than the nominal voltage and tolerate up to 30× more errors over an SNR range of 3dB to 8dB, while maintaining less than 3× degradation in BER. This is equivalent with energy savings of 45.7% compared to conventional LDPC decoders, and 33.2% compared to a sign bit protected LDPC decoder." @default.
- W2113231699 created "2016-06-24" @default.
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- W2113231699 date "2012-10-01" @default.
- W2113231699 modified "2023-09-23" @default.
- W2113231699 title "Energy-Efficient LDPC Decoders Based on Error-Resiliency" @default.
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- W2113231699 doi "https://doi.org/10.1109/sips.2012.60" @default.
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