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• W2113253469 abstract "As power has become the pre-eminent design constraint for future HPC systems, computational efficiency is being emphasized over simply peak performance. Recently, static benchmark codes have been used to find a power efficient architecture. Unfortunately, because compilers generate sub-optimal code, benchmark performance can be a poor indicator of the performance potential of architecture design points. Therefore, we present hardware/software cotuning as a novel approach for system design, in which traditional architecture space exploration is tightly coupled with software auto-tuning for delivering substantial improvements in area and power efficiency. We demonstrate the proposed methodology by exploring the parameter space of a Tensilica-based multi-processor running three of the most heavily used kernels in scientific computing, each with widely varying micro-architectural requirements: sparse matrix vector multiplication, stencil-based computations, and general matrix-matrix multiplication. Results demonstrate that co-tuning significantly improves hardware area and energy efficiency -- a key driver for next generation of HPC system design." @default.
• W2113253469 created "2016-06-24" @default.
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• W2113253469 date "2009-11-14" @default.
• W2113253469 modified "2023-09-27" @default.
• W2113253469 title "A design methodology for domain-optimized power-efficient supercomputing" @default.
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• W2113253469 doi "https://doi.org/10.1145/1654059.1654072" @default.
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