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- W2113301757 abstract "The pseudo-MOS transistor technique is useful for quick and accurate characterization of as-fabricated silicon-on-insulator wafers. The sample size and probe-pressure effects on the drain current are revisited. It is demonstrated that the geometrical factor is significantly affected by the probe-to-edge distance and probe pressure. The correct geometrical factor, reflecting silicon island size, and probe pressure effects, is extracted from systematic experimental results and used to determine the actual carrier mobility." @default.
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- W2113301757 date "2005-03-01" @default.
- W2113301757 modified "2023-09-23" @default.
- W2113301757 title "Detailed Investigation of Geometrical Factor for Pseudo-MOS Transistor Technique" @default.
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- W2113301757 doi "https://doi.org/10.1109/ted.2005.843970" @default.
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