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- W2113358566 abstract "Nonvolatile Memories (NVMs) can undergo different types of disturbances. These disturbances are particular to the technology and the cell structure of the memory element. In this paper we develop a coupling fault model that appropriately models disturbances in flash memories that use floating gate transistor as their core memory element. We describe the behavior of faulty cells under different fault models and how their characteristics change under each model. We demonstrate the inappropriateness of conventional march algorithms for testing flash memories and present a procedure to derive pseudo-algorithms that can be used in testing flash memories. In addition we present an efficient test that detects these disturbances under different fault models developed in this paper." @default.
- W2113358566 created "2016-06-24" @default.
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- W2113358566 date "2002-11-13" @default.
- W2113358566 modified "2023-10-11" @default.
- W2113358566 title "Flash memory disturbances: modeling and test" @default.
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- W2113358566 doi "https://doi.org/10.1109/vts.2001.923442" @default.
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