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• W2113458531 abstract "In this paper, the influence of the clock slope on the speed of various classes of flip-flops (FFs) and on the overall energy dissipation of both FFs and clock domain buffers is analyzed. Analysis shows that an optimum clock slope exists, which minimizes the energy spent in a clock domain. Results show that the clock slope requirement can be relaxed with respect to traditional assumptions, leading up to 30 ÷40 % energy savings and at a very small speed performance penalty. The effectiveness of the clock slope optimization is discussed in detail for the existing classes of FFs. The impact of such an optimization in terms of additive skew and jitter contributions is discussed, together to the analysis of the impact of technology scaling. Extensive post-layout simulations on a 65-nm CMOS technology are performed to check the validity of the underlying assumptions and approximations." @default.
• W2113458531 created "2016-06-24" @default.
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• W2113458531 creator A5052037141 @default.
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• W2113458531 date "2010-06-01" @default.
• W2113458531 modified "2023-10-16" @default.
• W2113458531 title "Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design" @default.
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• W2113458531 doi "https://doi.org/10.1109/tcsi.2009.2030113" @default.
• W2113458531 hasPublicationYear "2010" @default.
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