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- W2113692904 abstract "Several approaches have been proposed to accelerate the NP-complete Boolean Satisfiability problem (SAT) using reconfigurable computing. In this paper, we present a five-stage pipelined SAT solver. SAT solving is broken into five stages: variable decision, variable effect fetch, clause evaluation, conflict detection, and conflict analysis. The solver performs a novel search algorithm combining state-of-the-art SAT solvers advanced techniques: non-chronological backjumping, dynamic backtracking and learning without explicit traversal of implication graph. SAT instance information is stored into FPGA block RAMs avoiding synthesizing overhead for each instance. The proposed solver achieves up to 70× speedup over other hardware SAT solvers with 200× less resource utilization." @default.
- W2113692904 created "2016-06-24" @default.
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- W2113692904 date "2011-03-01" @default.
- W2113692904 modified "2023-10-18" @default.
- W2113692904 title "A reconfigurable, pipelined, conflict directed jumping search SAT solver" @default.
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- W2113692904 doi "https://doi.org/10.1109/date.2011.5763199" @default.
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