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- W2114601314 abstract "This paper presents a high-speed 1:2 demultiplexer (DEMUX) implemented in a 0.18-mum CMOS process. By employing a capacitive-splitting architecture for the current-mode-logic latches, a significant speed improvement is achieved in the proposed DEMUX. Provided a 2 <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>23</sup> - 1 pseudorandom bit sequence from the pattern generator, the fabricated circuit operates at an input data rate up to 20 Gb/s. The fully integrated DEMUX consumes a dc power of 150 mW from a 2-V supply voltage." @default.
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- W2114601314 date "2007-08-01" @default.
- W2114601314 modified "2023-09-25" @default.
- W2114601314 title "A 20-Gb/s 1 : 2 Demultiplexer With Capacitive-Splitting Current-Mode-Logic Latches" @default.
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- W2114601314 doi "https://doi.org/10.1109/tmtt.2007.902071" @default.
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