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• W2114618374 abstract "To ensure the quality of manufactured integrated circuits, it is important that designs be delay fault testable. A formal verification technique such as temporal logic can help avoid the large cost of dynamic simulation. Temporal logic is a formalism for evaluating the temporal behavior of systems. STeP, Stanford Temporal Prover, is a system developed at Stanford University to support computer-aided formal verification of concurrent and reactive systems based on temporal logic specification. The application of temporal logic and STeP to delay fault testability modeling and analysis is presented." @default.
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• W2114618374 date "2002-11-22" @default.
• W2114618374 modified "2023-09-25" @default.
• W2114618374 title "Delay fault testability modeling with temporal logic" @default.
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• W2114618374 doi "https://doi.org/10.1109/autest.1997.633648" @default.
• W2114618374 hasPublicationYear "2002" @default.
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