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• W2114740146 abstract "A low-power single-chip RISC microprocessor has been designed. It based on Hitachi's SH architecture with multiple page-size MMU. An automatic-power-save cache memory reduces the power dissipation at low frequencies, Two low-power modes and a module-stop function are software programmable for system power management. MMU supports 4 KB and 1 KB page-sizes by 4-way set-associative TLB. The chip using 0.5 um CMOS technology is fabricated, and achieves 60 Dhrystone MIPS and keeps 600 mW (max.), 60 MHz at worst condition." @default.
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• W2114740146 date "2002-11-19" @default.
• W2114740146 modified "2023-09-26" @default.
• W2114740146 title "A low-power single-chip microprocessor with multiple page-size MMU for nomadic computing" @default.
• W2114740146 cites W2544077880 @default.
• W2114740146 doi "https://doi.org/10.1109/vlsic.1995.520684" @default.
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