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• W2114996876 abstract "In this paper, we present a new memory, 3-transistor flash (3-Tr), which is suited to the embedded application. The memory cell has inherited low power the erase/program characteristic of the NAND flash. The cell size of the 32kByte 3-Tr flash, fabricated in a 0.4um NAND flash technology, is 4.36 /spl mu/m/sup 2/. This is about 1/8 of the EEPROM cell size having the same design rule. We also propose two circuit technologies, a low power sensing scheme and a double stage boosting scheme (DSB). The sense scheme aims to reduce the power of the read operation without degrading access time. DSB, on the other hand, improves the power consumption property of the word line (WL) decoder during the program mode. It is also immune to a decrease of the supply voltage Vdd." @default.
• W2114996876 created "2016-06-24" @default.
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• W2114996876 date "2002-11-07" @default.
• W2114996876 modified "2023-09-26" @default.
• W2114996876 title "A 60 ns access 32 kByte 3-transistor flash for low power embedded applications" @default.
• W2114996876 cites W1480073886 @default.
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• W2114996876 doi "https://doi.org/10.1109/vlsic.2000.852879" @default.
• W2114996876 hasPublicationYear "2002" @default.
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