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- W2115086768 abstract "A 16*16-bit complex multiplier using self-aligned gate GaAs heterostructure FET technology has been demonstrated. The multiplier uses a modified Booth's algorithm and three stages of pipeline with an embedded accumulator to allow the computation of a complex multiply function. A total of 4500 gates and over 20000 devices are required to implement this function and self-test functions. The chip produces a 20-bit output allowing 40 bits to describe a complex number result. Direct coupled NOR-gate FET logic was used throughout. The complex multiplier operated at a clock rate of 520 MHz with a power dissipation of 4 W under self-test. This corresponds to an average 'loaded' gate delay of 96 ps at 0.89 mW/gate. It also means that the multiplier produces a complex product, generated using four real multiplications and two additions, in less than 8 ns. This result demonstrates the high-speed capability of LSI digital circuits fabricated using MBE-grown GaAs heterostructure FET technology.< <ETX xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>></ETX>" @default.
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- W2115086768 date "1989-10-01" @default.
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- W2115086768 title "A 500-MHz 16*16 complex multiplier using self-aligned gate GaAs heterostructure FET technology" @default.
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