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• W2115306409 abstract "An approach for technology mapping using cell generators and CMOS dynamic logic circuits is given. The algorithm, based on a hierarchical synchronous network graph representation, is applicable to both combinatorial and sequential circuit descriptions. The target realization is in the form of NORA pipelined data paths and is therefore most appropriate for DSP applications. >" @default.
• W2115306409 created "2016-06-24" @default.
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• W2115306409 creator A5070292543 @default.
• W2115306409 date "2002-12-30" @default.
• W2115306409 modified "2023-09-26" @default.
• W2115306409 title "Technology mapping algorithms for NORA dynamic logic circuits" @default.
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• W2115306409 doi "https://doi.org/10.1109/edac.1993.386457" @default.
• W2115306409 hasPublicationYear "2002" @default.
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