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- W2115308217 abstract "This paper presents efficient testing methodologies for conditional sum adders. A conditional sum adder consists of conditional cells and selection cells. We propose a design-for-testability (DFT) technique to modify the conditional cells of a conditional sum adder. Then a test scheme is used for detecting the conditional sum adder with single cell fault model (CFM). The proposed test scheme only needs very low-test complexity to test a conditional sum adder. For example, the number of test patterns for a 64-bit conditional sum adder is only 9. The ratio of the number of test patterns of the proposed test scheme to the number of the test patterns of the previous scheme (Becker et al., 1995) is only about 1%. Also, experimental results show that the area overhead is only about 2.8% for a 64-bit conditional sum adder with the DFT scheme." @default.
- W2115308217 created "2016-06-24" @default.
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- W2115308217 date "2005-04-06" @default.
- W2115308217 modified "2023-09-23" @default.
- W2115308217 title "Efficient Test Methodologies for Conditional Sum Adders" @default.
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- W2115308217 doi "https://doi.org/10.1109/ats.2004.40" @default.
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