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• W2115449380 abstract "The Discrete Fourier Transform (DFT) can be viewed as the Fourier Transform of a periodic and regularly sampled signal. The Non-Uniform Discrete Fourier Transform (NuDFT) is a generalization of the DFT for data that may not be regularly sampled in spatial or temporal dimensions. This flexibility allows for benefits in situation where sensor placement cannot be guaranteed to be regular or where prior knowledge of the informational content could allow for better sampling patterns than a regular one. NuDFT is used in applications such as Synthetic Aperture Radar (SAR), Computed Tomography (CT), and Magnetic Resonance Imaging (MRI). Direct calculation of NDFT is time consuming and, in general, Non-uniform Fast Fourier Transform (NuFFT) is used. The key of computing NuFFT is to interpolate the non-uniformly sampled data onto a uniform grid and then use the Fast Fourier Transform. The interpolation process, called re-gridding or data-translation, is known to be the most time consuming (over 90% of the overall computation time of NuFFT) [1]. FPGA have been shown in prior work to be a power efficient way to perform this re-gridding as in [1]. We propose a novel memory-efficient FPGA based technique based on grouping the source points together in on-chip memory and hence reducing the number of memory accesses. The proposed architecture exhibits high performance for the re-gridding process. A speed-up of over 7.5 X was achieved when compared with existing FPGA-based technique for a target grid of size 256 atimes; 256. The basic procedure for re-gridding is based on updating all the target points within a specified distance of the source point using an interpolation kernel function. In this paper, we refer to this specified distance as interpolation threshold and its value is expressed in terms of the number of target points. Our proposed architecture is based on dividing the 2- Dimensional (2D) uniform target grid T into smaller 2D sub-grid. These sub-grids are called tiles. Corresponding to each tile, a block memory based FIFO is used. The idea is to group the source points that affect a tile into the FIFO corresponding to the tile. FIFOs are read one at a time and the tile corresponding to the FIFO being read is fetched from the external memory into the device. Performance of the proposed architecture is evaluated by simulating and computing the number of clock cycles required. Using a clock frequency of 50 MHz, which is chosen to be less then the achieved maximum frequency of 60.16 MHz, computation time for the translation process is calculated. Based on this computed time, throughput is calculated in terms of frames per second (fps)." @default.
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• W2115449380 date "2014-05-11" @default.
• W2115449380 modified "2023-09-26" @default.
• W2115449380 title "Memory Optimized Re-gridding for Non-uniform Fast Fourier Transform on FPGAs" @default.
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