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- W2115710931 abstract "RECFEC is a REConfigurable processor optimized for soft implementation of Forward Error Correction (FEC) algorithms. Viterbi, Turbo, Reed-Solomon and LDPC coding algorithms are widely used in wired and wireless standards. The implantation of these algorithms on RECFEC for a multi-mode wireless system is explored and performance metrics are demonstrated. RECFEC is comprised of a pool of processing elements, a processing element controller and memory. Each processing element encapsulates multiple functional units which are optimized for FEC algorithms. Memory includes the configuration and the data buffers. A high bandwidth interconnect network facilitates data movements. Unlike traditional approach to programmable FEC architectures, RECFEC supports multiple algorithms and is instruction-level programmable which results the ultimate flexibility and programmability." @default.
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- W2115710931 date "2008-03-01" @default.
- W2115710931 modified "2023-10-16" @default.
- W2115710931 title "RECFEC: A Reconfigurable FEC Processor for Viterbi, Turbo, Reed-Solomon and LDPC Coding" @default.
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- W2115710931 doi "https://doi.org/10.1109/wcnc.2008.112" @default.
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