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- W2115959869 abstract "We describe a platform based design methodology for system-on-a-chip (SOC). An embedded 32-bit RISC CPU and a field-programmable gate array (FPGA) are used to implement applications that require both a program running on the CPU and hardware acceleration performed by the FPGA. The methodology consists of flow and tools for hardware/software partitioning, hardware accelerator design/synthesis, software compilation, interface generation, integrated hardware/software cosimulation, and system verification. We also present a case of implementing an image decoder in a hardware/software codesign fashion on the platform. Experimental results show that the methodology is indeed effective for IP development/verification and fast prototyping." @default.
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- W2115959869 date "2005-01-01" @default.
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- W2115959869 title "A platform based SOC design methodology and its application in image compression" @default.
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- W2115959869 doi "https://doi.org/10.1504/ijes.2005.008806" @default.
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