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- W2116012944 abstract "This paper discusses electrical design of off chip and on-chip interconnects. Modeling and Simulation CAD tools used for this design are identified and described. The focus of the paper is on off-chip interconnects, which are loosely referred to as packaging structures. These may be single-chip package interconnects, or connections between chips in a multiple-chip system, and include chip electrical connections (bondwires, C4, etc.) and package or connector pins/bumps. Phenomena which are critical to error-free product performance are discussed, and alternative methods of modeling and simulating these phenomena are presented. Similarities and differences of on-chip and off-chip interconnect characteristics are noted when appropriate." @default.
- W2116012944 created "2016-06-24" @default.
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- W2116012944 date "2002-12-17" @default.
- W2116012944 modified "2023-09-27" @default.
- W2116012944 title "Modeling and simulation of package and interconnects" @default.
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- W2116012944 doi "https://doi.org/10.1109/bipol.1994.587855" @default.
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