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- W2116200605 abstract "The FFT processor is the most speed critical part in the multi-carrier orthogonal frequency division multiplexing (OFDM) communication system. In these systems, low power is usually one of the major concerns. We propose a memory based recursive FFT design in FPGA for the low power base-band OFDM transmitter and receiver for WiMax (Wireless Metropolitan Area Network) application. It is implemented by radix-8 FFT. As results, the power consumption will be reduced by 28% compared to radix-4 FFT [1]. The proposed architecture has three advantages: (1) fewer butterfly iterations to reduce power consumption, (2) pipeline of radix-8 butterfly to speed up clock frequency, (3) even distribution of memory access to make the best utilization efficiency of SRAM ports.." @default.
- W2116200605 created "2016-06-24" @default.
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- W2116200605 date "2006-09-22" @default.
- W2116200605 modified "2023-09-23" @default.
- W2116200605 title "Reconfigurable FFT Design for Low Power OFDM Communication Systems" @default.
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- W2116200605 doi "https://doi.org/10.1109/isce.2006.1689473" @default.
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