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- W2116710910 abstract "The factors that determine the routability of high-density gate array (HDGA) logic designs are analyzed. The base array, leaf cells, and placement and routing software are optimized for routability. Design for routability reduces chip area, cost, and turnaround time. The surface areas of experimental designs are less than those of conventional standard-cell designs with similar performance. The base array, leaf cells, and placement and routing software are optimized for routability. An HDGA version of a 10*10-b fully-pipelined multiplier is designed both in a three-metal layer technology and a technology with two metal layers and straps. The resulting HDGA implementations are equal in area and show very similar performance to a SC version with two metal layers. >" @default.
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- W2116710910 date "2002-12-04" @default.
- W2116710910 modified "2023-10-02" @default.
- W2116710910 title "Design for routability of a high-density gate array" @default.
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- W2116710910 doi "https://doi.org/10.1109/iccd.1990.130160" @default.
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