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- W2116732528 abstract "This paper addresses the issues of automating the derivation of test configurations (TCs) for both local and global interconnect of SRAM-based FPGAs. We model FPGA interconnect and their test requirements using adjacency graphs and obtain the minimal or near minimal TO by solving the graph coloring problem, using a modified greedy algorithm. We apply the proposed modeling and TC derivation method to the Xilinx XC4000 FPGA. A set of minimal TCs was derived automatically. The proposed method is applicable to FPGAs of various interconnect structures and sizes, and supports distinctive test logic." @default.
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- W2116732528 date "2003-06-26" @default.
- W2116732528 modified "2023-09-25" @default.
- W2116732528 title "Modeling of FPGA local/global interconnect resources and derivation of minimal test configurations" @default.
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- W2116732528 doi "https://doi.org/10.1109/dftvs.2002.1173525" @default.
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