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• W2116734185 abstract "Silicon nanowires (Si NWs) are promising candidates for field-effect transistor (FET) conduction channel. Planar configuration using a back gate is an easy way to study these devices. We demonstrate the possibility to build high performance FET using a simple silicidation process leading to high effective holes' mobility between 130 cm 2 ⋅V -1 ⋅s -1 and 200 cm 2 ⋅V -1 ⋅s -1 and good I ON /I OFF ratio up to 10 5 . Moreover we investigated the possibility to passivate the NWs using either a high-k dielectric layer or a thermal oxide shell around the NWs. This leads to a reduction of the hysteretic behavior during the gate voltage sweep from 30 V to 1 V depending on the material and the gate configuration." @default.
• W2116734185 created "2016-06-24" @default.
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• W2116734185 date "2012-08-01" @default.
• W2116734185 modified "2023-10-18" @default.
• W2116734185 title "ELECTRICAL CHARACTERIZATION OF PLANAR SILICON NANOWIRE FIELD-EFFECT TRANSISTORS" @default.
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• W2116734185 doi "https://doi.org/10.1142/s0219581x1240011x" @default.
• W2116734185 hasPublicationYear "2012" @default.
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