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- W2116760475 abstract "LVDS has become a popular choice for high-speed serial links in large-sized display units. This work presents the design and implementation of I/O interface circuits for Gbps operation which is fully complied with the IEEE STD. 1596.3 (LVDS). A step-down voltage regulator is employed to reject the noise coupled in the system power supply. A CMFB (common mode feedback) circuitry is utilized in the transmitter to stabilize the common mode voltage in a predefined range. By contrast, a regenerative circuit which provides a positive feedback loop gain between the preamplifier and the output buffer in the receiver. A typical 0.25 /spl mu/m 1P5M CMOS technology is used to realize the proposed LVDS transceiver. The post-layout simulation reveals that the data rate is 1.0 Gbps at all process corners." @default.
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- W2116760475 date "2004-10-26" @default.
- W2116760475 modified "2023-09-27" @default.
- W2116760475 title "1.0 Gbps LVDS transceiver design for LCD panels" @default.
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- W2116760475 doi "https://doi.org/10.1109/apasic.2004.1349459" @default.
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