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• W2116777461 abstract "Latency-insensitive protocols allow system-on-chip (SoC) engineers to decouple the design of the computing cores from the design of the intercore communication channels while following the synchronous design paradigm. In a latency-insensitive system (LIS), each core is encapsulated within a shell, which is a synthesized interface module that dynamically controls its operation. At each clock period, if new data have not arrived on an input channel or if a stalling request has arrived on an output channel, the shell stalls the core and buffers other incoming valid data for future processing. The combination of finite buffers and backpressure from stalling can cause throughput degradation. Previous works addressed this problem by increasing buffer space to reduce the backpressure requests or inserting extra buffering to balance the channel latency around a LIS. We explore the theoretical complexity of these approaches and propose a heuristic algorithm for efficient queue sizing (QS). We evaluate the heuristic algorithm with experiments over a large set of synthetically generated systems and with a case study of a real SoC system. We find that the topology of a LIS can impact not only how much throughput degradation will occur but also the difficulty of finding optimal QS solutions." @default.
• W2116777461 created "2016-06-24" @default.
• W2116777461 creator A5069945847 @default.
• W2116777461 creator A5086038041 @default.
• W2116777461 date "2008-12-01" @default.
• W2116777461 modified "2023-09-26" @default.
• W2116777461 title "Topology-Based Performance Analysis and Optimization of Latency-Insensitive Systems" @default.
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• W2116777461 doi "https://doi.org/10.1109/tcad.2008.2008914" @default.
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