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- W2117041600 abstract "This paper describes a number of microarchitectural techniques for supporting multithreading in soft processor cores. These include a new thread scheduler that combines interleaved and block multithreading; a table of operation latencies (TOOL) for determining instruction latencies; support of arbitrary-latency custom computational units; and a multibanked register file for supporting simultaneous write-back operations from different threads. Our results show that four-way, multithreaded, processors achieve speedups of up to 26% over a single-threaded processor executing benchmarks that only use regular instructions, and up to 47% when executing benchmarks that include long-latency instructions." @default.
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- W2117041600 date "2007-08-01" @default.
- W2117041600 modified "2023-09-27" @default.
- W2117041600 title "Microarchitectural Enhancements for Configurable Multi-Threaded Soft Processors" @default.
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- W2117041600 doi "https://doi.org/10.1109/fpl.2007.4380768" @default.
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