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- W2117507633 abstract "In this paper, we present a new algorithm to construct a discrete Voronoi diagram based on the Euclidean distance metric in a binary image. The algorithm has linear time complexity and is suited to very large-scale integration (VLSI) implementation due to the use of local neighborhood calculations on reduced bit-width data. A cellular architecture for construction of the diagram is proposed. The proposed architecture has been implemented in VLSI using 0.35 micron 2-poly 3-metal layer complementary metal-oxide-semiconductor technology, and the dimensions of the chip are 3.16 mm/spl times/3.16 mm, with the maximum frequency of operation being 50 MHz." @default.
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- W2117507633 date "2004-04-01" @default.
- W2117507633 modified "2023-10-16" @default.
- W2117507633 title "A High-Speed VLSI Design and ASIC Implementation for Constructing Euclidean Distance-Based Discrete Voronoi Diagram" @default.
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- W2117507633 doi "https://doi.org/10.1109/tra.2004.824638" @default.
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