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- W2117519967 abstract "The paper presents an automatic procedure for generating a particular kind of extended finite state machine, which allows a more uniform exploration of the state space of a design under verification. The proposed approach avoids the transition-incompatibility problem which typically arises in actual HW/SW-system descriptions. A EFSM-based ATPG, which exploits such a model, is able to more uniformly analyze the state space of the system with respect to using a generic EFSM." @default.
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- W2117519967 date "2010-10-01" @default.
- W2117519967 modified "2023-10-18" @default.
- W2117519967 title "Effective EFSM generation for HW/SW-design verification" @default.
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- W2117519967 doi "https://doi.org/10.1109/bec.2010.5631006" @default.
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