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- W2117653492 abstract "A three-dimensional (3-D) integration technology based on the wafer-to-wafer bonding using through silicon vias (TSV's) has been developed for the fabrication of new 3-D LSIs. A 3-D image sensor chip, 3-D shared memory chip, 3-D artificial retina chip and 3-D microprocessor test chip have been fabricated by using this technology. In addition, we have proposed a new reconfigurable parallel image processing system. To achieve this system, we have proposed a new 3-D integration technology based on multichip-to-wafer bonding called a super-chip integration. Many chips are simultaneously aligned and bonded onto lower chips using a self-assembly technique in a super-chip integration." @default.
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- W2117653492 date "2009-01-19" @default.
- W2117653492 modified "2023-09-24" @default.
- W2117653492 title "Three-dimensional integration technology and integrated systems" @default.
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- W2117653492 doi "https://doi.org/10.5555/1509633.1509735" @default.
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