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- W2117741503 abstract "A general form and a set of basic gates in implementing two-level (K+1)-valued logic circuits are presented. A complete fault analysis on the proposed circuit shows that all fanout stem faults can be collapsed to branch faults. A procedure is derived, based on the fault relationships obtained for fault collapsing. Results show that for a two-level (K+1)-valued logic circuit, faults can be reduced to 19% of the original total faults. >" @default.
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- W2117741503 date "2003-01-02" @default.
- W2117741503 modified "2023-09-23" @default.
- W2117741503 title "Fault analysis on two-level (K+1)-valued logic circuits" @default.
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- W2117741503 doi "https://doi.org/10.1109/ismvl.1992.186793" @default.
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