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• W2117831059 abstract "A fractional-N phase-locked loop (PLL) serves as a Gaussian minimum-shift keying (GMSK) transmitter and a receive frequency synthesizer for GSM. The entire transmitter/synthesizer is fully integrated in 0.35-μm CMOS and consumes 17.4 and 12 mW from 2.5 V in the transmit and receive modes, respectively, including an on-chip voltage-controlled oscillator. The circuit meets GSM specifications on modulation accuracy in transmit mode, and measured phase noise from the closed-loop PLL is -148 dBc/Hz and -162 dBc/Hz, respectively, at 3- and 20-MHz offset. Worst case spur at 13-MHz offset is -77 dBc." @default.
• W2117831059 created "2016-06-24" @default.
• W2117831059 creator A5028638391 @default.
• W2117831059 creator A5038877867 @default.
• W2117831059 date "2003-05-01" @default.
• W2117831059 modified "2023-09-23" @default.
• W2117831059 title "A 17-mW transmitter and frequency synthesizer for 900-MHz GSM fully integrated in 0.35μm CMOS" @default.
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• W2117831059 doi "https://doi.org/10.1109/jssc.2003.810052" @default.
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