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- W2117966973 abstract "Synthesis of asynchronous logic using the tool Petrify requires a state graph with a complete state coding. It is common for specifications to exhibit concurrent outputs, but Petrify is sometimes unable to resolve the state coding conflicts that arise as a result, and hence cannot synthesise a circuit. A pair of decomposition heuristics (expressed in the language of Delay-Insensitive Sequential Processes) are given that helps one to obtain a synthesisable specification. The second heuristic has been successfully applied to a set of nine benchmarks to obtain significant reductions both in area and in synthesis time, compared with synthesis performed on the original specifications." @default.
- W2117966973 created "2016-06-24" @default.
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- W2117966973 date "2004-06-07" @default.
- W2117966973 modified "2023-10-18" @default.
- W2117966973 title "Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis" @default.
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- W2117966973 doi "https://doi.org/10.1145/996566.996788" @default.
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