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• W2117997243 abstract "A new design methodology for a pattern generator is proposed, formulated in the context of on-chip BIST. The design methodology is circuit-specific and uses synthesis techniques to design BIST generators. The pattern generator consists of two components: a pseudorandom pattern generator (like an LFSR or, preferably, a GLFSR) and a combinational logic to map the outputs of the pseudorandom pattern generator. This combinational logic is synthesized to produce a given set of target patterns by mapping the outputs of the pseudorandom pattern generator. It is shown that, for a particular CUT, an area-efficient combinational logic block can be designed/synthesized to achieve 100 (or almost 100) percent single stuck-at fault coverage using a small number of test the This method is significantly different from weighted pattern generation and can guarantee testing of all hard-to-detect faults without expensive test point insertion. Experimental results on common benchmark netlists demonstrate that the fault coverage of the proposed pattern generator is significantly higher compared to conventional pattern generation techniques. The design technique for the logic mapper is unique and can be used effectively to improve existing pattern generators for combinational logic and scan-based BIST structures." @default.
• W2117997243 created "2016-06-24" @default.
• W2117997243 creator A5000575551 @default.
• W2117997243 creator A5070343644 @default.
• W2117997243 date "2003-12-01" @default.
• W2117997243 modified "2023-09-27" @default.
• W2117997243 title "A BIST pattern generator design for near-perfect fault coverage" @default.
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• W2117997243 doi "https://doi.org/10.1109/tc.2003.1252851" @default.
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